/* gt64120a.h - Galileo gt64120A bridge device header */

/* Copyright 1984-2002 Wind River Systems, Inc. */

/*
modification history
--------------------
01c,07oct04,pes  Apigen cleanup
01b,26apr02,dat  Adding cplusplus protection, SPR 75017
01a,15jun00,dra	 Written from earlier Galileo version of BSP.
*/

/*
* This file contains register offsets and programming values for the
* GT64120A bridge chip, which appears on the Galileo Technologies ev64120a
* evaluation board.
*/

/* Copyright (c) Galileo Technology Inc. All rights reserved.
 *
 * THIS SOFTWARE IS PROVIDED BY GALILEO TECHNOLOGY INC. ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL GALILEO TECHNOLOGY INC. BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 * ANY REDISTRIBUTION OF THIS SOURCE CODE MUST RETAIN THE COPYRIGHT AND
 * DECLARATION STATED ABOVE.
 *
 */

#ifndef __INCgt64120ah
#define __INCgt64120ah

#ifdef __cplusplus
extern "C" {
#endif

/*
*********************************************************************
*
* GT64120A Internal Register OFFSETS
*
*********************************************************************
*/

/* CPU Configuration */
#define GT_CPU_INTF_CFG_OFS			0x000
#define GT_MULTI_GT_REG_OFS			0x120

/* CPU Address Decode */
#define GT_SCS10_L_DEC_ADRS_OFS			0x008
#define GT_SCS10_H_DEC_ADRS_OFS			0x010
#define GT_SCS32_L_DEC_ADRS_OFS			0x018
#define GT_SCS32_H_DEC_ADRS_OFS			0x020
#define GT_CS20_L_DEC_ADRS_OFS			0x028
#define GT_CS20_H_DEC_ADRS_OFS			0x030
#define GT_CS3_BOOTCS_L_DEC_ADRS_OFS		0x038
#define GT_CS3_BOOTCS_H_DEC_ADRS_OFS		0x040
#define GT_PCI0_IO_L_DEC_ADRS_OFS		0x048
#define GT_PCI0_IO_H_DEC_ADRS_OFS		0x050
#define GT_PCI0_MEM_0_L_DEC_ADRS_OFS		0x058
#define GT_PCI0_MEM_0_H_DEC_ADRS_OFS		0x060
#define GT_PCI0_MEM_1_L_DEC_ADRS_OFS		0x080
#define GT_PCI0_MEM_1_H_DEC_ADRS_OFS		0x088
#define GT_PCI1_IO_L_DEC_ADRS_OFS		0x090
#define GT_PCI1_IO_H_DEC_ADRS_OFS		0x098
#define GT_PCI1_MEM_0_L_DEC_ADRS_OFS		0x0a0
#define GT_PCI1_MEM_0_H_DEC_ADRS_OFS		0x0a8
#define GT_PCI1_MEM_1_L_DEC_ADRS_OFS		0x0b0
#define GT_PCI1_MEM_1_H_DEC_ADRS_OFS		0x0b8
#define GT_INTERNAL_SPACE_DEC_OFS		0x068
#define GT_SCS10_ADRS_REMAP_OFS			0x0d0
#define GT_SCS32_ADRS_REMAP_OFS			0x0d8
#define GT_CS20_REMAP_OFS			0x0e0
#define GT_CS3_BOOTCS_REMAP_OFS			0x0e8
#define GT_PCI0_IO_REMAP_OFS			0x0f0
#define GT_PCI0_MEM_0_REMAP_OFS			0x0f8
#define GT_PCI0_MEM_1_REMAP_OFS			0x100
#define GT_PCI1_IO_REMAP_OFS			0x108
#define GT_PCI1_MEM_0_REMAP_OFS			0x110
#define GT_PCI1_MEM_1_REMAP_OFS			0x118

/* CPU Errors Report */
#define GT_CPU_ERROR_ADRS_L_OFS			0x070
#define GT_CPU_ERROR_ADRS_H_OFS			0x078
#define GT_CPU_ERROR_DATA_L_OFS			0x128
#define GT_CPU_ERROR_DATA_H_OFS			0x130
#define GT_CPU_ERROR_PARITY_OFS			0x138

/* CPU Sync Barrier */
#define GT_PCI0_SYNC_BARRIER_VIRT_OFS		0x0c0
#define GT_PCI1_SYNC_BARRIER_VIRT_OFS		0x0c8

/* SDRAM and Device Address Decode */
#define GT_SCS0_L_DEC_ADRS_OFS			0x400
#define GT_SCS0_H_DEC_ADRS_OFS			0x404
#define GT_SCS1_L_DEC_ADRS_OFS			0x408
#define GT_SCS1_H_DEC_ADRS_OFS			0x40c
#define GT_SCS2_L_DEC_ADRS_OFS			0x410
#define GT_SCS2_H_DEC_ADRS_OFS			0x414
#define GT_SCS3_L_DEC_ADRS_OFS			0x418
#define GT_SCS3_H_DEC_ADRS_OFS			0x41c
#define GT_CS0_L_DEC_ADRS_OFS			0x420
#define GT_CS0_H_DEC_ADRS_OFS			0x424
#define GT_CS1_L_DEC_ADRS_OFS			0x428
#define GT_CS1_H_DEC_ADRS_OFS			0x42c
#define GT_CS2_L_DEC_ADRS_OFS			0x430
#define GT_CS2_H_DEC_ADRS_OFS			0x434
#define GT_CS3_L_DEC_ADRS_OFS			0x438
#define GT_CS3_H_DEC_ADRS_OFS			0x43c
#define GT_BOOTCS_L_DEC_ADRS_OFS		0x440
#define GT_BOOTCS_H_DEC_ADRS_OFS		0x444
#define GT_ADRS_DEC_ERROR_OFS			0x470

/* SDRAM Configuration */
#define GT_SDRAM_CFG_OFS			0x448
#define GT_SDRAM_OP_MODE_OFS			0x474
#define GT_SDRAM_BURST_MODE_OFS			0x478
#define GT_SDRAM_ADRS_DEC_OFS			0x47c

/* SDRAM Parameters */
#define GT_SDRAM_BANK0_PARAM_OFS		0x44c
#define GT_SDRAM_BANK1_PARAM_OFS		0x450
#define GT_SDRAM_BANK2_PARAM_OFS		0x454
#define GT_SDRAM_BANK3_PARAM_OFS		0x458

/* ECC */
#define GT_ECC_ERROR_ADRS_OFS			0x490
#define GT_ECC_ERROR_DATA_H_OFS			0x480
#define GT_ECC_ERROR_DATA_L_OFS			0x484
#define GT_ECC_FROM_MEM_OFS			0x488
#define GT_ECC_CALCULATED_OFS			0x48c

/* Device Parameters*/
#define GT_DEV_BANK0_PARAM_OFS			0x45c
#define GT_DEV_BANK1_PARAM_OFS			0x460
#define GT_DEV_BANK2_PARAM_OFS			0x464
#define GT_DEV_BANK3_PARAM_OFS			0x468
#define GT_DEV_BOOT_BANK_PARAM_OFS		0x46c

/* DMA Record */
#define GT_CHAN_0_DMA_BYTE_COUNT_OFS		0x800
#define GT_CHAN_1_DMA_BYTE_COUNT_OFS		0x804
#define GT_CHAN_2_DMA_BYTE_COUNT_OFS		0x808
#define GT_CHAN_3_DMA_BYTE_COUNT_OFS		0x80c
#define GT_CHAN_0_DMA_SRC_ADRS_OFS		0x810
#define GT_CHAN_1_DMA_SRC_ADRS_OFS		0x814
#define GT_CHAN_2_DMA_SRC_ADRS_OFS		0x818
#define GT_CHAN_3_DMA_SRC_ADRS_OFS		0x81c
#define GT_CHAN_0_DMA_DEST_ADRS_OFS		0x820
#define GT_CHAN_1_DMA_DEST_ADRS_OFS		0x824
#define GT_CHAN_2_DMA_DEST_ADRS_OFS		0x828
#define GT_CHAN_3_DMA_DEST_ADRS_OFS		0x82c
#define GT_CHAN_0_NEXT_REC_PTR_OFS		0x830
#define GT_CHAN_1_NEXT_REC_PTR_OFS		0x834
#define GT_CHAN_2_NEXT_REC_PTR_OFS		0x838
#define GT_CHAN_3_NEXT_REC_PTR_OFS		0x83c
#define GT_CHAN_0_CURRENT_DESCRIPTOR_PTR_OFS	0x870
#define GT_CHAN_1_CURRENT_DESCRIPTOR_PTR_OFS	0x874
#define GT_CHAN_2_CURRENT_DESCRIPTOR_PTR_OFS	0x878
#define GT_CHAN_3_CURRENT_DESCRIPTOR_PTR_OFS	0x87c
#define GT_CHAN_0_CTL_OFS			0x840
#define GT_CHAN_1_CTL_OFS			0x844
#define GT_CHAN_2_CTL_OFS			0x848
#define GT_CHAN_3_CTL_OFS			0x84c

/* DMA Arbiter */
#define GT_ARBITER_CTL_OFS			0x860

/* Timer/COUNTER */
#define GT_TIMER_COUNTER_0_OFS			0x850
#define GT_TIMER_COUNTER_1_OFS			0x854
#define GT_TIMER_COUNTER_2_OFS			0x858
#define GT_TIMER_COUNTER_3_OFS			0x85c
#define GT_TIMER_COUNTER_CTL_OFS		0x864

/* PCI Internal */
#define GT_PCI0_COMMAND_OFS			0xc00
#define GT_PCI1_COMMAND_OFS			0xc80
#define GT_PCI0_TIMEOUT_RETRY_OFS		0xc04
#define GT_PCI1_TIMEOUT_RETRY_OFS		0xc84
#define GT_PCI0_SCS10_BANK_SZ_OFS		0xc08
#define GT_PCI1_SCS10_BANK_SZ_OFS		0xc88
#define GT_PCI0_SCS32_BANK_SZ_OFS		0xc0c
#define GT_PCI1_SCS32_BANK_SZ_OFS		0xc8c
#define GT_PCI0_CS20_BANK_SZ_OFS		0xc10
#define GT_PCI1_CS20_BANK_SZ_OFS		0xc90
#define GT_PCI0_CS3_BOOTCS_BANK_SZ_OFS		0xc14
#define GT_PCI1_CS3_BOOTCS_BANK_SZ_OFS		0xc94
#define GT_PCI0_BASE_ADRS_REGS_ENABLE_OFS	0xc3c
#define GT_PCI1_BASE_ADRS_REGS_ENABLE_OFS	0xcbc
#define GT_PCI0_PREFETCH_MAX_BURST_SZ_OFS	0xc40
#define GT_PCI1_PREFETCH_MAX_BURST_SZ_OFS	0xcc0
#define GT_PCI0_SCS10_BASE_ADRS_REMAP_OFS	0xc48
#define GT_PCI1_SCS10_BASE_ADRS_REMAP_OFS	0xcc8
#define GT_PCI0_SCS32_BASE_ADRS_REMAP_OFS	0xc4c
#define GT_PCI1_SCS32_BASE_ADRS_REMAP_OFS	0xccc
#define GT_PCI0_CS20_BASE_ADRS_REMAP_OFS	0xc50
#define GT_PCI1_CS20_BASE_ADRS_REMAP_OFS	0xcd0
#define GT_PCI0_CS3_BOOTCS_BASE_ADRS_REMAP_OFS	0xc54
#define GT_PCI1_CS3_BOOTCS_BASE_ADRS_REMAP_OFS	0xcd4
#define GT_PCI0_SWAPPED_SCS10_BASE_ADRS_REMAP_OFS	0xc58
#define GT_PCI1_SWAPPED_SCS10_BASE_ADRS_REMAP_OFS	0xcd8
#define GT_PCI0_SWAPPED_SCS32_BASE_ADRS_REMAP_OFS	0xc5c
#define GT_PCI1_SWAPPED_SCS32_BASE_ADRS_REMAP_OFS	0xcdc
#define GT_PCI0_SWAPPED_CS3_BOOTCS_BASE_ADRS_REMAP_OFS	0xc64
#define GT_PCI1_SWAPPED_CS3_BOOTCS_BASE_ADRS_REMAP_OFS	0xce4
#define GT_PCI0_CFG_ADRS_OFS			0xcf8
#define GT_PCI1_CFG_ADRS_OFS			0xcf0
#define GT_PCI0_CFG_DATA_VIRT_OFS		0xcfc
#define GT_PCI1_CFG_DATA_VIRT_OFS		0xcf4
#define GT_PCI0_INTR_ACK_VIRT_OFS		0xc34
#define GT_PCI1_INTR_ACK_VIRT_OFS		0xc30

/* Interrupts */
#define GT_INTR_CAUSE_OFS			0xc18
#define GT_H_INTR_CAUSE_OFS			0xc98
#define GT_CPU_INTR_MASK_OFS			0xc1c
#define GT_CPU_H_INTR_MASK_OFS			0xc9c
#define GT_PCI0_INTR_CAUSE_MASK_OFS		0xc24
#define GT_PCI0_H_INTR_CAUSE_MASK_OFS		0xca4
#define GT_PCI0_SERR0_MASK_OFS			0xc28
#define GT_PCI1_SERR1_MASK_OFS			0xca8
#define GT_CPU_SELECT_CAUSE_OFS			0xc70
#define GT_PCI0_INTR_SELECT_OFS			0xc74

/*
 * PCI Configuration
 * 
 * This is done by writing a register offset from pciConfigLib.h into
 * GT_PCI0_CFG_ADRS, and then writing or reading the register value at
 * GT_PCI0_CFG_DATA_VIRT.  For register offsets, use definitions from
 * pciConfigLib.h
 *
 * for PCI1, use GT_PCI1_CFG_{ADRS,DATA_VIRT}. Alternatively, add the
 * constant offset GT_PCI1_CFG_OFS to the register offset, and use
 * GT_PCI0_CFG_{ADRS,DATA_VIRT}
 */

#define GT_PCI1_CFG_OFS				0x080

#define GT_PCI0_SCS10_BASE_ADRS_OFS		PCI_CFG_BASE_ADDRESS_0
#define GT_PCI0_SCS32_BASE_ADRS_OFS		PCI_CFG_BASE_ADDRESS_1
#define GT_PCI0_CS20_BASE_ADRS_OFS		PCI_CFG_BASE_ADDRESS_2
#define GT_PCI0_CS3_BOOTCS_BASE_ADRS_OFS	PCI_CFG_BASE_ADDRESS_3
#define GT_PCI0_INTERNAL_REGS_MEM_MAPPED_BASE_ADRS_OFS	PCI_CFG_BASE_ADDRESS_4
#define GT_PCI0_INTERNAL_REGS_IO_MAPPED_BASE_ADRS_OFS	PCI_CFG_BASE_ADDRESS_5
#define GT_EXPANSION_ROM_BASE_ADRS_OFS		PCI_CFG_EXPANSION_ROM

/* PCI Configuration, Function 1 */
#define GT_PCI0_SWAPPED_SCS10_BASE_ADRS_OFS	0x110
#define GT_PCI0_SWAPPED_SCS32_BASE_ADRS_OFS	0x114
#define GT_PCI0_SWAPPED_CS3_BOOTCS_BASE_ADRS_OFS	0x11c

/* I2O Support Registers */
#define GT_INBOUND_MESSAGE_0_OFS		0x10
#define GT_INBOUND_MESSAGE_1_OFS		0x14
#define GT_OUTBOUND_MESSAGE_0_OFS		0x18
#define GT_OUTBOUND_MESSAGE_1_OFS		0x1c
#define GT_INBOUND_DOORBELL_OFS			0x20
#define GT_INBOUND_INTR_CAUSE_OFS		0x24
#define GT_INBOUND_INTR_MASK_OFS			0x28
#define GT_OUTBOUND_DOORBELL_OFS		0x2c
#define GT_OUTBOUND_INTR_CAUSE_OFS		0x30
#define GT_OUTBOUND_INTR_MASK_OFS		0x34
#define GT_INBOUND_QUEUE_PORT_VIRT_OFS		0x40
#define GT_OUTBOUND_QUEUE_PORT_VIRT_OFS		0x44
#define GT_QUEUE_CTL_OFS			0x50
#define GT_QUEUE_BASE_ADRS_OFS			0x54
#define GT_INBOUND_FREE_HEAD_PTR_OFS		0x60
#define GT_INBOUND_FREE_TAIL_PTR_OFS		0x64
#define GT_INBOUND_POST_HEAD_PTR_OFS		0x68
#define GT_INBOUND_POST_TAIL_PTR_OFS		0x6c
#define GT_OUTBOUND_FREE_HEAD_PTR_OFS		0x70
#define GT_OUTBOUND_FREE_TAIL_PTR_OFS		0x74
#define GT_OUTBOUND_POST_HEAD_PTR_OFS		0x78
#define GT_OUTBOUND_POST_TAIL_PTR_OFS		0x7c


/*
*********************************************************************
*
* GT64120A Internal Register ABSOLUTE ADDRESSES
*
* These require the includer of this header to define a GT_BASE macro.
* Here's an assembly-language example:
*
*   #include <gt64120a.h>
*
*   #define K1BASE	0xa0000000	/@ MIPS base address for phys mem @/
*   #define GT_BASE	(K1BASE | GT_INTERNAL_REGS_BASE_DEF)
*
*	   lw	   k0,GT_CPU_INTF_CFG	/@ get CPU Interface Configuration @/
*
*********************************************************************
*/

/* Default memory map */

#define GT_SCS0_BASE_DEF		0x00000000
#define GT_SCS1_BASE_DEF		0x00800000
#define GT_SCS2_BASE_DEF		0x01000000
#define GT_SCS3_BASE_DEF		0x01800000
#define GT_PCI0_IO_0_BASE_DEF		0x10000000
#define GT_PCI0_MEM_0_BASE_DEF		0x12000000
#define GT_INTERNAL_REGS_BASE_DEF	0x14000000
#define GT_CS0_BASE_DEF			0x1c000000
#define GT_CS1_BASE_DEF			0x1c800000
#define GT_CS2_BASE_DEF			0x1d000000
#define GT_CS3_BASE_DEF			0x1f000000
#define GT_BOOTCS_BASE_DEF		0x1fc00000
#define GT_PCI1_IO_BASE_DEF		0x20000000
#define GT_PCI1_MEM_0_BASE_DEF		0x22000000
#define GT_PCI1_MEM_1_BASE_DEF		0x24000000
#define GT_PCI0_MEM_1_BASE_DEF		0xf2000000

/* CPU Configuration */
#define GT_CPU_INTF_CFG			(GT_BASE+GT_CPU_INTF_CFG_OFS)
#define GT_MULTI_GT_REG			(GT_BASE+GT_MULTI_GT_REG_OFS)

/* CPU Address Decode */
#define GT_SCS10_L_DEC_ADRS		(GT_BASE+GT_SCS10_L_DEC_ADRS_OFS)
#define GT_SCS10_H_DEC_ADRS		(GT_BASE+GT_SCS10_H_DEC_ADRS_OFS)
#define GT_SCS32_L_DEC_ADRS		(GT_BASE+GT_SCS32_L_DEC_ADRS_OFS)
#define GT_SCS32_H_DEC_ADRS		(GT_BASE+GT_SCS32_H_DEC_ADRS_OFS)
#define GT_CS20_L_DEC_ADRS		(GT_BASE+GT_CS20_L_DEC_ADRS_OFS)
#define GT_CS20_H_DEC_ADRS		(GT_BASE+GT_CS20_H_DEC_ADRS_OFS)
#define GT_CS3_BOOTCS_L_DEC_ADRS	(GT_BASE+GT_CS3_BOOTCS_L_DEC_ADRS_OFS)
#define GT_CS3_BOOTCS_H_DEC_ADRS	(GT_BASE+GT_CS3_BOOTCS_H_DEC_ADRS_OFS)
#define GT_PCI0_IO_L_DEC_ADRS		(GT_BASE+GT_PCI0_IO_L_DEC_ADRS_OFS)
#define GT_PCI0_IO_H_DEC_ADRS		(GT_BASE+GT_PCI0_IO_H_DEC_ADRS_OFS)
#define GT_PCI0_MEM_0_L_DEC_ADRS	(GT_BASE+GT_PCI0_MEM_0_L_DEC_ADRS_OFS)
#define GT_PCI0_MEM_0_H_DEC_ADRS	(GT_BASE+GT_PCI0_MEM_0_H_DEC_ADRS_OFS)
#define GT_PCI0_MEM_1_L_DEC_ADRS	(GT_BASE+GT_PCI0_MEM_1_L_DEC_ADRS_OFS)
#define GT_PCI0_MEM_1_H_DEC_ADRS	(GT_BASE+GT_PCI0_MEM_1_H_DEC_ADRS_OFS)
#define GT_PCI1_IO_L_DEC_ADRS		(GT_BASE+GT_PCI1_IO_L_DEC_ADRS_OFS)
#define GT_PCI1_IO_H_DEC_ADRS		(GT_BASE+GT_PCI1_IO_H_DEC_ADRS_OFS)
#define GT_PCI1_MEM_0_L_DEC_ADRS	(GT_BASE+GT_PCI1_MEM_0_L_DEC_ADRS_OFS)
#define GT_PCI1_MEM_0_H_DEC_ADRS	(GT_BASE+GT_PCI1_MEM_0_H_DEC_ADRS_OFS)
#define GT_PCI1_MEM_1_L_DEC_ADRS	(GT_BASE+GT_PCI1_MEM_1_L_DEC_ADRS_OFS)
#define GT_PCI1_MEM_1_H_DEC_ADRS	(GT_BASE+GT_PCI1_MEM_1_H_DEC_ADRS_OFS)
#define GT_INTERNAL_SPACE_DEC		(GT_BASE+GT_INTERNAL_SPACE_DEC_OFS)
#define GT_SCS10_ADRS_REMAP		(GT_BASE+GT_SCS10_ADRS_REMAP_OFS)
#define GT_SCS32_ADRS_REMAP		(GT_BASE+GT_SCS32_ADRS_REMAP_OFS)
#define GT_CS20_REMAP			(GT_BASE+GT_CS20_REMAP_OFS)
#define GT_CS3_BOOTCS_REMAP		(GT_BASE+GT_CS3_BOOTCS_REMAP_OFS)
#define GT_PCI0_IO_REMAP		(GT_BASE+GT_PCI0_IO_REMAP_OFS)
#define GT_PCI0_MEM_0_REMAP		(GT_BASE+GT_PCI0_MEM_0_REMAP_OFS)
#define GT_PCI0_MEM_1_REMAP		(GT_BASE+GT_PCI0_MEM_1_REMAP_OFS)
#define GT_PCI1_IO_REMAP		(GT_BASE+GT_PCI1_IO_REMAP_OFS)
#define GT_PCI1_MEM_0_REMAP		(GT_BASE+GT_PCI1_MEM_0_REMAP_OFS)
#define GT_PCI1_MEM_1_REMAP		(GT_BASE+GT_PCI1_MEM_1_REMAP_OFS)

/* CPU Errors Report */
#define GT_CPU_ERROR_ADRS_L		(GT_BASE+GT_CPU_ERROR_ADRS_L_OFS)
#define GT_CPU_ERROR_ADRS_H		(GT_BASE+GT_CPU_ERROR_ADRS_H_OFS)
#define GT_CPU_ERROR_DATA_L		(GT_BASE+GT_CPU_ERROR_DATA_L_OFS)
#define GT_CPU_ERROR_DATA_H		(GT_BASE+GT_CPU_ERROR_DATA_H_OFS)
#define GT_CPU_ERROR_PARITY		(GT_BASE+GT_CPU_ERROR_PARITY_OFS)

/* CPU Sync Barrier */
#define GT_PCI0_SYNC_BARRIER_VIRT	(GT_BASE+GT_PCI0_SYNC_BARRIER_VIRT_OFS)
#define GT_PCI1_SYNC_BARRIER_VIRT	(GT_BASE+GT_PCI1_SYNC_BARRIER_VIRT_OFS)

/* SDRAM and Device Address Decode */
#define GT_SCS0_L_DEC_ADRS		(GT_BASE+GT_SCS0_L_DEC_ADRS_OFS)
#define GT_SCS0_H_DEC_ADRS		(GT_BASE+GT_SCS0_H_DEC_ADRS_OFS)
#define GT_SCS1_L_DEC_ADRS		(GT_BASE+GT_SCS1_L_DEC_ADRS_OFS)
#define GT_SCS1_H_DEC_ADRS		(GT_BASE+GT_SCS1_H_DEC_ADRS_OFS)
#define GT_SCS2_L_DEC_ADRS		(GT_BASE+GT_SCS2_L_DEC_ADRS_OFS)
#define GT_SCS2_H_DEC_ADRS		(GT_BASE+GT_SCS2_H_DEC_ADRS_OFS)
#define GT_SCS3_L_DEC_ADRS		(GT_BASE+GT_SCS3_L_DEC_ADRS_OFS)
#define GT_SCS3_H_DEC_ADRS		(GT_BASE+GT_SCS3_H_DEC_ADRS_OFS)
#define GT_CS0_L_DEC_ADRS		(GT_BASE+GT_CS0_L_DEC_ADRS_OFS)
#define GT_CS0_H_DEC_ADRS		(GT_BASE+GT_CS0_H_DEC_ADRS_OFS)
#define GT_CS1_L_DEC_ADRS		(GT_BASE+GT_CS1_L_DEC_ADRS_OFS)
#define GT_CS1_H_DEC_ADRS		(GT_BASE+GT_CS1_H_DEC_ADRS_OFS)
#define GT_CS2_L_DEC_ADRS		(GT_BASE+GT_CS2_L_DEC_ADRS_OFS)
#define GT_CS2_H_DEC_ADRS		(GT_BASE+GT_CS2_H_DEC_ADRS_OFS)
#define GT_CS3_L_DEC_ADRS		(GT_BASE+GT_CS3_L_DEC_ADRS_OFS)
#define GT_CS3_H_DEC_ADRS		(GT_BASE+GT_CS3_H_DEC_ADRS_OFS)
#define GT_BOOTCS_L_DEC_ADRS		(GT_BASE+GT_BOOTCS_L_DEC_ADRS_OFS)
#define GT_BOOTCS_H_DEC_ADRS		(GT_BASE+GT_BOOTCS_H_DEC_ADRS_OFS)
#define GT_ADRS_DEC_ERROR		(GT_BASE+GT_ADRS_DEC_ERROR_OFS)

/* SDRAM Configuration */
#define GT_SDRAM_CFG			(GT_BASE+GT_SDRAM_CFG_OFS)
#define GT_SDRAM_OP_MODE		(GT_BASE+GT_SDRAM_OP_MODE_OFS)
#define GT_SDRAM_BURST_MODE		(GT_BASE+GT_SDRAM_BURST_MODE_OFS)
#define GT_SDRAM_ADRS_DEC		(GT_BASE+GT_SDRAM_ADRS_DEC_OFS)

/* SDRAM Parameters */
#define GT_SDRAM_BANK0_PARAM		(GT_BASE+GT_SDRAM_BANK0_PARAM_OFS)
#define GT_SDRAM_BANK1_PARAM		(GT_BASE+GT_SDRAM_BANK1_PARAM_OFS)
#define GT_SDRAM_BANK2_PARAM		(GT_BASE+GT_SDRAM_BANK2_PARAM_OFS)
#define GT_SDRAM_BANK3_PARAM		(GT_BASE+GT_SDRAM_BANK3_PARAM_OFS)

/* ECC */
#define GT_ECC_ERROR_ADRS		(GT_BASE+GT_ECC_ERROR_ADRS_OFS)
#define GT_ECC_ERROR_DATA_H		(GT_BASE+GT_ECC_ERROR_DATA_H_OFS)
#define GT_ECC_ERROR_DATA_L		(GT_BASE+GT_ECC_ERROR_DATA_L_OFS)
#define GT_ECC_FROM_MEM			(GT_BASE+GT_ECC_FROM_MEM_OFS)
#define GT_ECC_CALCULATED		(GT_BASE+GT_ECC_CALCULATED_OFS)

/* Device Parameters*/
#define GT_DEV_BANK0_PARAM		(GT_BASE+GT_DEV_BANK0_PARAM_OFS)
#define GT_DEV_BANK1_PARAM		(GT_BASE+GT_DEV_BANK1_PARAM_OFS)
#define GT_DEV_BANK2_PARAM		(GT_BASE+GT_DEV_BANK2_PARAM_OFS)
#define GT_DEV_BANK3_PARAM		(GT_BASE+GT_DEV_BANK3_PARAM_OFS)
#define GT_DEV_BOOT_BANK_PARAM		(GT_BASE+GT_DEV_BOOT_BANK_PARAM_OFS)

/* DMA Record */
#define GT_CHAN_0_DMA_BYTE_COUNT	(GT_BASE+GT_CHAN_0_DMA_BYTE_COUNT_OFS)
#define GT_CHAN_1_DMA_BYTE_COUNT	(GT_BASE+GT_CHAN_1_DMA_BYTE_COUNT_OFS)
#define GT_CHAN_2_DMA_BYTE_COUNT	(GT_BASE+GT_CHAN_2_DMA_BYTE_COUNT_OFS)
#define GT_CHAN_3_DMA_BYTE_COUNT	(GT_BASE+GT_CHAN_3_DMA_BYTE_COUNT_OFS)
#define GT_CHAN_0_DMA_SRC_ADRS		(GT_BASE+GT_CHAN_0_DMA_SRC_ADRS_OFS)
#define GT_CHAN_1_DMA_SRC_ADRS		(GT_BASE+GT_CHAN_1_DMA_SRC_ADRS_OFS)
#define GT_CHAN_2_DMA_SRC_ADRS		(GT_BASE+GT_CHAN_2_DMA_SRC_ADRS_OFS)
#define GT_CHAN_3_DMA_SRC_ADRS		(GT_BASE+GT_CHAN_3_DMA_SRC_ADRS_OFS)
#define GT_CHAN_0_DMA_DEST_ADRS		(GT_BASE+GT_CHAN_0_DMA_DEST_ADRS_OFS)
#define GT_CHAN_1_DMA_DEST_ADRS		(GT_BASE+GT_CHAN_1_DMA_DEST_ADRS_OFS)
#define GT_CHAN_2_DMA_DEST_ADRS		(GT_BASE+GT_CHAN_2_DMA_DEST_ADRS_OFS)
#define GT_CHAN_3_DMA_DEST_ADRS		(GT_BASE+GT_CHAN_3_DMA_DEST_ADRS_OFS)
#define GT_CHAN_0_NEXT_REC_PTR		(GT_BASE+GT_CHAN_0_NEXT_REC_PTR_OFS)
#define GT_CHAN_1_NEXT_REC_PTR		(GT_BASE+GT_CHAN_1_NEXT_REC_PTR_OFS)
#define GT_CHAN_2_NEXT_REC_PTR		(GT_BASE+GT_CHAN_2_NEXT_REC_PTR_OFS)
#define GT_CHAN_3_NEXT_REC_PTR		(GT_BASE+GT_CHAN_3_NEXT_REC_PTR_OFS)
#define GT_CHAN_0_CURRENT_DESCRIPTOR_PTR	(GT_BASE+GT_CHAN_0_CURRENT_DESCRIPTOR_PTR_OFS)
#define GT_CHAN_1_CURRENT_DESCRIPTOR_PTR	(GT_BASE+GT_CHAN_1_CURRENT_DESCRIPTOR_PTR_OFS)
#define GT_CHAN_2_CURRENT_DESCRIPTOR_PTR	(GT_BASE+GT_CHAN_2_CURRENT_DESCRIPTOR_PTR_OFS)
#define GT_CHAN_3_CURRENT_DESCRIPTOR_PTR	(GT_BASE+GT_CHAN_3_CURRENT_DESCRIPTOR_PTR_OFS)
#define GT_CHAN_0_CTL			(GT_BASE+GT_CHAN_0_CTL_OFS)
#define GT_CHAN_1_CTL			(GT_BASE+GT_CHAN_1_CTL_OFS)
#define GT_CHAN_2_CTL			(GT_BASE+GT_CHAN_2_CTL_OFS)
#define GT_CHAN_3_CTL			(GT_BASE+GT_CHAN_3_CTL_OFS)

/* DMA Arbiter */
#define GT_ARBITER_CTL			(GT_BASE+GT_ARBITER_CTL_OFS)

/* Timer/COUNTER */
#define GT_TIMER_COUNTER_0		(GT_BASE+GT_TIMER_COUNTER_0_OFS)
#define GT_TIMER_COUNTER_1		(GT_BASE+GT_TIMER_COUNTER_1_OFS)
#define GT_TIMER_COUNTER_2		(GT_BASE+GT_TIMER_COUNTER_2_OFS)
#define GT_TIMER_COUNTER_3		(GT_BASE+GT_TIMER_COUNTER_3_OFS)
#define GT_TIMER_COUNTER_CTL		(GT_BASE+GT_TIMER_COUNTER_CTL_OFS)

/* PCI Internal */
#define GT_PCI0_COMMAND			(GT_BASE+GT_PCI0_COMMAND_OFS)
#define GT_PCI1_COMMAND			(GT_BASE+GT_PCI1_COMMAND_OFS)
#define GT_PCI0_TIMEOUT_RETRY		(GT_BASE+GT_PCI0_TIMEOUT_RETRY_OFS)
#define GT_PCI1_TIMEOUT_RETRY		(GT_BASE+GT_PCI1_TIMEOUT_RETRY_OFS)
#define GT_PCI0_SCS10_BANK_SZ		(GT_BASE+GT_PCI0_SCS10_BANK_SZ_OFS)
#define GT_PCI1_SCS10_BANK_SZ		(GT_BASE+GT_PCI1_SCS10_BANK_SZ_OFS)
#define GT_PCI0_SCS32_BANK_SZ		(GT_BASE+GT_PCI0_SCS32_BANK_SZ_OFS)
#define GT_PCI1_SCS32_BANK_SZ		(GT_BASE+GT_PCI1_SCS32_BANK_SZ_OFS)
#define GT_PCI0_CS20_BANK_SZ		(GT_BASE+GT_PCI0_CS20_BANK_SZ_OFS)
#define GT_PCI1_CS20_BANK_SZ		(GT_BASE+GT_PCI1_CS20_BANK_SZ_OFS)
#define GT_PCI0_CS3_BOOTCS_BANK_SZ	(GT_BASE+GT_PCI0_CS3_BOOTCS_BANK_SZ_OFS)
#define GT_PCI1_CS3_BOOTCS_BANK_SZ	(GT_BASE+GT_PCI1_CS3_BOOTCS_BANK_SZ_OFS)
#define GT_PCI0_BASE_ADRS_REGS_ENABLE	(GT_BASE+GT_PCI0_BASE_ADRS_REGS_ENABLE_OFS)
#define GT_PCI1_BASE_ADRS_REGS_ENABLE	(GT_BASE+GT_PCI1_BASE_ADRS_REGS_ENABLE_OFS)
#define GT_PCI0_PREFETCH_MAX_BURST_SZ	(GT_BASE+GT_PCI0_PREFETCH_MAX_BURST_SZ_OFS)
#define GT_PCI1_PREFETCH_MAX_BURST_SZ	(GT_BASE+GT_PCI1_PREFETCH_MAX_BURST_SZ_OFS)
#define GT_PCI0_SCS10_BASE_ADRS_REMAP	(GT_BASE+GT_PCI0_SCS10_BASE_ADRS_REMAP_OFS)
#define GT_PCI1_SCS10_BASE_ADRS_REMAP	(GT_BASE+GT_PCI1_SCS10_BASE_ADRS_REMAP_OFS)
#define GT_PCI0_SCS32_BASE_ADRS_REMAP	(GT_BASE+GT_PCI0_SCS32_BASE_ADRS_REMAP_OFS)
#define GT_PCI1_SCS32_BASE_ADRS_REMAP	(GT_BASE+GT_PCI1_SCS32_BASE_ADRS_REMAP_OFS)
#define GT_PCI0_CS20_BASE_ADRS_REMAP	(GT_BASE+GT_PCI0_CS20_BASE_ADRS_REMAP_OFS)
#define GT_PCI1_CS20_BASE_ADRS_REMAP	(GT_BASE+GT_PCI1_CS20_BASE_ADRS_REMAP_OFS)
#define GT_PCI0_CS3_BOOTCS_BASE_ADRS_REMAP	(GT_BASE+GT_PCI0_CS3_BOOTCS_BASE_ADRS_REMAP_OFS)
#define GT_PCI1_CS3_BOOTCS_BASE_ADRS_REMAP	(GT_BASE+GT_PCI1_CS3_BOOTCS_BASE_ADRS_REMAP_OFS)
#define GT_PCI0_SWAPPED_SCS10_BASE_ADRS_REMAP	(GT_BASE+GT_PCI0_SWAPPED_SCS10_BASE_ADRS_REMAP_OFS)
#define GT_PCI1_SWAPPED_SCS10_BASE_ADRS_REMAP	(GT_BASE+GT_PCI1_SWAPPED_SCS10_BASE_ADRS_REMAP_OFS)
#define GT_PCI0_SWAPPED_SCS32_BASE_ADRS_REMAP	(GT_BASE+GT_PCI0_SWAPPED_SCS32_BASE_ADRS_REMAP_OFS)
#define GT_PCI1_SWAPPED_SCS32_BASE_ADRS_REMAP	(GT_BASE+GT_PCI1_SWAPPED_SCS32_BASE_ADRS_REMAP_OFS)
#define GT_PCI0_SWAPPED_CS3_BOOTCS_BASE_ADRS_REMAP	(GT_BASE+GT_PCI0_SWAPPED_CS3_BOOTCS_BASE_ADRS_REMAP_OFS)
#define GT_PCI1_SWAPPED_CS3_BOOTCS_BASE_ADRS_REMAP	(GT_BASE+GT_PCI1_SWAPPED_CS3_BOOTCS_BASE_ADRS_REMAP_OFS)
#define GT_PCI0_CFG_ADRS		(GT_BASE+GT_PCI0_CFG_ADRS_OFS)
#define GT_PCI1_CFG_ADRS		(GT_BASE+GT_PCI1_CFG_ADRS_OFS)
#define GT_PCI0_CFG_DATA_VIRT		(GT_BASE+GT_PCI0_CFG_DATA_VIRT_OFS)
#define GT_PCI1_CFG_DATA_VIRT		(GT_BASE+GT_PCI1_CFG_DATA_VIRT_OFS)
#define GT_PCI0_INTR_ACK_VIRT		(GT_BASE+GT_PCI0_INTR_ACK_VIRT_OFS)
#define GT_PCI1_INTR_ACK_VIRT		(GT_BASE+GT_PCI1_INTR_ACK_VIRT_OFS)

/* Interrupts */
#define GT_INTR_CAUSE			(GT_BASE+GT_INTR_CAUSE_OFS)
#define GT_H_INTR_CAUSE			(GT_BASE+GT_H_INTR_CAUSE_OFS)
#define GT_CPU_INTR_MASK		(GT_BASE+GT_CPU_INTR_MASK_OFS)
#define GT_CPU_H_INTR_MASK		(GT_BASE+GT_CPU_H_INTR_MASK_OFS)
#define GT_PCI0_INTR_CAUSE_MASK		(GT_BASE+GT_PCI0_INTR_CAUSE_MASK_OFS)
#define GT_PCI0_H_INTR_CAUSE_MASK	(GT_BASE+GT_PCI0_H_INTR_CAUSE_MASK_OFS)
#define GT_PCI0_SERR0_MASK		(GT_BASE+GT_PCI0_SERR0_MASK_OFS)
#define GT_PCI1_SERR1_MASK		(GT_BASE+GT_PCI1_SERR1_MASK_OFS)
#define GT_CPU_SELECT_CAUSE		(GT_BASE+GT_CPU_SELECT_CAUSE_OFS)
#define GT_PCI0_INTR_SELECT		(GT_BASE+GT_PCI0_INTR_SELECT_OFS)

/*
 * I2O Support Registers
 *
 * "I20 registers can be accessed from the CPU and PCI_0 sides (unless
 * stated otherwise). If accessed from the PCI_0 side, address offset is
 * with respect to the PCI_0 SCS[1:0]* Base Address Register contents.
 * If accessed from the CPU side, the address offset is with respect to
 * the CPU Internal Space Base Register + 0x1c00"
 *			-- GT64120A Data Sheet Revision 1.0 p. 171
 */

#define GT_I2O_CPU_BASE_OFS		0x1c00

#define GT_INBOUND_MESSAGE_0		(GT_BASE+GT_I2O_CPU_BASE_OFS+GT_INBOUND_MESSAGE_0_OFS)
#define GT_INBOUND_MESSAGE_1		(GT_BASE+GT_I2O_CPU_BASE_OFS+GT_INBOUND_MESSAGE_1_OFS)
#define GT_OUTBOUND_MESSAGE_0		(GT_BASE+GT_I2O_CPU_BASE_OFS+GT_OUTBOUND_MESSAGE_0_OFS)
#define GT_OUTBOUND_MESSAGE_1		(GT_BASE+GT_I2O_CPU_BASE_OFS+GT_OUTBOUND_MESSAGE_1_OFS)
#define GT_INBOUND_DOORBELL		(GT_BASE+GT_I2O_CPU_BASE_OFS+GT_INBOUND_DOORBELL_OFS)
#define GT_INBOUND_INTR_CAUSE		(GT_BASE+GT_I2O_CPU_BASE_OFS+GT_INBOUND_INTR_CAUSE_OFS)
#define GT_INBOUND_INTR_MASK		(GT_BASE+GT_I2O_CPU_BASE_OFS+GT_INBOUND_INTR_MASK_OFS)
#define GT_OUTBOUND_DOORBELL		(GT_BASE+GT_I2O_CPU_BASE_OFS+GT_OUTBOUND_DOORBELL_OFS)
#define GT_OUTBOUND_INTR_CAUSE		(GT_BASE+GT_I2O_CPU_BASE_OFS+GT_OUTBOUND_INTR_CAUSE_OFS)
#define GT_OUTBOUND_INTR_MASK		(GT_BASE+GT_I2O_CPU_BASE_OFS+GT_OUTBOUND_INTR_MASK_OFS)
#define GT_INBOUND_QUEUE_PORT_VIRT	(GT_BASE+GT_I2O_CPU_BASE_OFS+GT_INBOUND_QUEUE_PORT_VIRT_OFS)
#define GT_OUTBOUND_QUEUE_PORT_VIRT	(GT_BASE+GT_I2O_CPU_BASE_OFS+GT_OUTBOUND_QUEUE_PORT_VIRT_OFS)
#define GT_QUEUE_CTL			(GT_BASE+GT_I2O_CPU_BASE_OFS+GT_QUEUE_CTL_OFS)
#define GT_QUEUE_BASE_ADRS		(GT_BASE+GT_I2O_CPU_BASE_OFS+GT_QUEUE_BASE_ADRS_OFS)
#define GT_INBOUND_FREE_HEAD_PTR	(GT_BASE+GT_I2O_CPU_BASE_OFS+GT_INBOUND_FREE_HEAD_PTR_OFS)
#define GT_INBOUND_FREE_TAIL_PTR	(GT_BASE+GT_I2O_CPU_BASE_OFS+GT_INBOUND_FREE_TAIL_PTR_OFS)
#define GT_INBOUND_POST_HEAD_PTR	(GT_BASE+GT_I2O_CPU_BASE_OFS+GT_INBOUND_POST_HEAD_PTR_OFS)
#define GT_INBOUND_POST_TAIL_PTR	(GT_BASE+GT_I2O_CPU_BASE_OFS+GT_INBOUND_POST_TAIL_PTR_OFS)
#define GT_OUTBOUND_FREE_HEAD_PTR	(GT_BASE+GT_I2O_CPU_BASE_OFS+GT_OUTBOUND_FREE_HEAD_PTR_OFS)
#define GT_OUTBOUND_FREE_TAIL_PTR	(GT_BASE+GT_I2O_CPU_BASE_OFS+GT_OUTBOUND_FREE_TAIL_PTR_OFS)
#define GT_OUTBOUND_POST_HEAD_PTR	(GT_BASE+GT_I2O_CPU_BASE_OFS+GT_OUTBOUND_POST_HEAD_PTR_OFS)
#define GT_OUTBOUND_POST_TAIL_PTR	(GT_BASE+GT_I2O_CPU_BASE_OFS+GT_OUTBOUND_POST_TAIL_PTR_OFS)

/*
**********************************************************************
*
* Register encodings
*
**********************************************************************
*/

/* create a mask of n ones */

#ifndef GT_MSK
#define GT_MSK(n)				((1 << (n)) - 1)
#endif


/* for CPU Interface Config: GT_CPU_INTF_CFG */

#define GT_CACHEOPMAP_SHF		0
#define GT_CACHEOPMAP_MSK		(GT_MSK(9) << GT_CACHEOPMAP_SHF)

#define GT_CACHEPRES_SHF		9
#define GT_CACHEPRES_MSK		(GT_MSK(1) << GT_CACHEPRES_SHF)
#define GT_CACHEPRES_BIT		GT_CACHEPRES_MSK
#define GT_CACHEPRES_GT64012_NOT_PRESENT	0
#define GT_CACHEPRES_GT64012_PRESENT	1

#define GT_WRITEMODE_SHF		11
#define GT_WRITEMODE_MSK		(GT_MSK(1) << GT_WRITEMODE_SHF)
#define GT_WRITEMODE_BIT		GT_WRITEMODE_MSK
#define GT_WRITEMODE_PIPELINED		0
#define GT_WRITEMODE_R4000		1

#define GT_ENDIANESS_SHF		12
#define GT_ENDIANESS_MSK		(GT_MSK(1) << GT_ENDIANESS_SHF)
#define GT_ENDIANESS_BIT		GT_ENDIANESS_MSK
#define GT_ENDIANESS_BIG		0
#define GT_ENDIANESS_LITTLE		1

#define GT_R5KL2_PRESENT_SHF		14
#define GT_R5KL2_PRESENT_MSK		(GT_MSK(1) << GT_R5KL2_PRESENT_SHF)
#define GT_R5KL2_PRESENT_BIT		GT_R5KL2_PRESENT_MSK
#define GT_R5KL2_PRESENT_NOT_PRESENT	0
#define GT_R5KL2_PRESENT_PRESENT	1

#define GT_EXTERNAL_HIT_DELAY_SHF	15
#define GT_EXTERNAL_HIT_DELAY_MSK	(GT_MSK(1) << GT_EXTERNAL_HIT_DELAY_SHF)
#define GT_EXTERNAL_HIT_DELAY_BIT	GT_EXTERNAL_HIT_DELAY_MSK
#define GT_EXTERNAL_HIT_DELAY_NON_REGISTERED	0
#define GT_EXTERNAL_HIT_DELAY_REGISTERED	1

#define GT_CPU_WRITE_RATE_SHF		16
#define GT_CPU_WRITE_RATE_MSK		(GT_MSK(1) << GT_CPU_WRITE_RATE_SHF)
#define GT_CPU_WRITE_RATE_BIT		GT_CPU_WRITE_RATE_MSK
#define GT_CPU_WRITE_RATE_DXDXDXDX	0
#define GT_CPU_WRITE_RATE_DDDD		1

#define GT_STOP_RETRY_SHF		17
#define GT_STOP_RETRY_MSK		(GT_MSK(1) << GT_STOP_RETRY_SHF)
#define GT_STOP_RETRY_BIT		GT_STOP_RETRY_MSK
#define GT_STOP_RETRY_CONTINUE		0
#define GT_STOP_RETRY_STOP		1

#define GT_MULTIGT_SHF			18
#define GT_MULTIGT_MSK			(GT_MSK(1) << GT_MULTIGT_SHF)
#define GT_MULTIGT_BIT			GT_MULTIGT_BIT
#define GT_MULTIGT_NOT_SUPPORTED	0
#define GT_MULTIGT_SUPPORTED		1

#define GT_SYSADCVALID_SHF		19
#define GT_SYSADCVALID_MSK		(GT_MSK(1) << GT_SYSADCVALID_SHF)
#define GT_SYSADCVALID_BIT		GT_SYSADCVALID_MSK
#define GT_SYSADCVALID_NOT_CONNECTED	0
#define GT_SYSADCVALID_CONNECTED	1

#define GT_PCI0OVERRIDE_SHF		20
#define GT_PCI0OVERRIDE_MSK		(GT_MSK(2) << GT_PCI0OVERRIDE_SHF)
#define GT_PCI0OVERRIDE_NORMAL		0	/* normal address decoding */
#define GT_PCI0OVERRIDE_1GBYTE		1	/* 1 GB PCI_0 Mem0 space */
#define GT_PCI0OVERRIDE_2GBYTE		2	/* 2 GB PCI_0 Mem0 space */

#define GT_PCI1OVERRIDE_SHF		24
#define GT_PCI1OVERRIDE_MSK		(GT_MSK(2) << GT_PCI1OVERRIDE_SHF)
#define GT_PCI1OVERRIDE_NORMAL		0	/* normal address decoding */
#define GT_PCI1OVERRIDE_1GBYTE		1	/* 1 GB PCI_1 Mem0 space */
#define GT_PCI1OVERRIDE_2GBYTE		2	/* 2 GB PCI_1 Mem0 space */


/*
 * for Internal Space Decode: GT_INTERNAL_SPACE_DEC
 */

#define GT_INTERNAL_SPACE_DEC_DEF	0x000000a0


/* for SDRAM Configuration: GT_SDRAM_CFG */

#define GT_SDRAM_CFG_REFINTCNT_SHF	0
#define GT_SDRAM_CFG_REFINTCNT_MSK	(GT_MSK(14) << GT_SDRAM_CFG_REFINTCNT_SHF)

#define GT_SDRAM_CFG_INTERLEAVE_SHF	14
#define GT_SDRAM_CFG_INTERLEAVE_MSK    (GT_MSK(1) << GT_SDRAM_CFG_INTERLEAVE_SHF)
#define GT_SDRAM_CFG_INTERLEAVE_BIT	GT_SDRAM_CFG_INTERLEAVE_MSK
#define GT_SDRAM_CFG_INTERLEAVE_ENABLED	0
#define GT_SDRAM_CFG_INTERLEAVE_DISABLED	1

#define GT_SDRAM_CFG_RMW_SHF		15
#define GT_SDRAM_CFG_RMW_MSK		(GT_MSK(1) << GT_SDRAM_CFG_RMW_SHF)
#define GT_SDRAM_CFG_RMW_BIT		GT_SDRAM_CFG_RMW_MSK
#define GT_SDRAM_CFG_RMW_DISABLED	0
#define GT_SDRAM_CFG_RMW_ENABLED	1

#define GT_SDRAM_CFG_STAGREF_SHF	16
#define GT_SDRAM_CFG_STAGREF_MSK	(GT_MSK(1) << GT_SDRAM_CFG_STAGREF_SHF)
#define GT_SDRAM_CFG_STAGREF_BIT	GT_SDRAM_CFG_STAGREF_MSK
#define GT_SDRAM_CFG_STAGREF_STAGGERED	0
#define GT_SDRAM_CFG_STAGREF_NON_STAGGERED	1

#define GT_SDRAM_CFG_CPUTODRAMERR_SHF	17
#define GT_SDRAM_CFG_CPUTODRAMERR_MSK	(GT_MSK(1) << GT_SDRAM_CFG_CPUTODRAMERR_SHF)
#define GT_SDRAM_CFG_CPUTODRAMERR_BIT	GT_SDRAM_CFG_CPUTODRAMERR_MSK
#define GT_SDRAM_CFG_CPUTODRAMERR_GENERATE_ERR	0
#define GT_SDRAM_CFG_CPUTODRAMERR_ALWAYS_GOOD	1

#define GT_SDRAM_CFG_ECCINT_SHF		18
#define GT_SDRAM_CFG_ECCINT_MSK		(GT_MSK(1) << GT_SDRAM_CFG_ECCINT_SHF)
#define GT_SDRAM_CFG_ECCINT_BIT		GT_SDRAM_CFG_ECCINT_MSK
#define GT_SDRAM_CFG_ECCINT_2_ERRORS	0
#define GT_SDRAM_CFG_ECCINT_1_ERROR	1

#define GT_SDRAM_CFG_DUPCNTL_SHF	19
#define GT_SDRAM_CFG_DUPCNTL_MSK	(GT_MSK(1) << GT_SDRAM_CFG_DUPCNTL_SHF)
#define GT_SDRAM_CFG_DUPCNTL_BIT	GT_SDRAM_CFG_DUPCNTL_MSK

#define GT_SDRAM_CFG_DUPBA_SHF		20
#define GT_SDRAM_CFG_DUPBA_MSK		(GT_MSK(1) << GT_SDRAM_CFG_DUPBA_SHF)
#define GT_SDRAM_CFG_DUPBA_BIT		GT_SDRAM_CFG_DUPBA_MSK
#define GT_SDRAM_CFG_DUPBA_DO_NOT_DUP	0
#define GT_SDRAM_CFG_DUPBA_DUPLICATE	1

#define GT_SDRAM_CFG_DUPEOT0_SHF	21
#define GT_SDRAM_CFG_DUPEOT0_MSK	(GT_MSK(1) << GT_SDRAM_CFG_DUPEOT0_SHF)
#define GT_SDRAM_CFG_DUPEOT0_BIT	GT_SDRAM_CFG_DUPEOT0_MSK
#define GT_SDRAM_CFG_DUPEOT0_DO_NOT_DUP	0
#define GT_SDRAM_CFG_DUPEOT0_DUPLICATE	1

#define GT_SDRAM_CFG_DUPEOT1_SHF	22
#define GT_SDRAM_CFG_DUPEOT1_MSK	(GT_MSK(1) << GT_SDRAM_CFG_DUPEOT1_SHF)
#define GT_SDRAM_CFG_DUPEOT1_BIT	GT_SDRAM_CFG_DUPEOT1_MSK
#define GT_SDRAM_CFG_DUPEOT1_DO_NOT_DUP	0
#define GT_SDRAM_CFG_DUPEOT1_DUPLICATE	1

#define GT_SDRAM_CFG_REGSDRAM_SHF	23
#define GT_SDRAM_CFG_REGSDRAM_MSK	(GT_MSK(1) << GT_SDRAM_CFG_REGSDRAM_SHF)
#define GT_SDRAM_CFG_REGSDRAM_BIT	GT_SDRAM_CFG_REGSDRAM_MSK
#define GT_SDRAM_CFG_REGSDRAM_DISABLE	0
#define GT_SDRAM_CFG_REGSDRAM_ENABLE	1

#define GT_SDRAM_CFG_DADR12_SHF		24
#define GT_SDRAM_CFG_DADR12_MSK		(GT_MSK(1) << GT_SDRAM_CFG_DADR12_SHF)
#define GT_SDRAM_CFG_DADR12_BIT		GT_SDRAM_CFG_DADR12_MSK
#define GT_SDRAM_CFG_DADR12_ADP0	0
#define GT_SDRAM_CFG_DADR12_DMAREQ3	0


/* for SDRAM Operation Mode: GT_SDRAM_OP_MODE */

#define GT_SDRAM_OPMODE_OP_SHF		0
#define GT_SDRAM_OPMODE_OP_MSK		(GT_MSK(3) << GT_SDRAM_OPMODE_OP_SHF)
#define GT_SDRAM_OPMODE_OP_NORMAL	0	/* Normal SDRAM mode */
#define GT_SDRAM_OPMODE_OP_NOP		1	/* NOP Command */
#define GT_SDRAM_OPMODE_OP_ABPC		2	/* All banks precharge cmd */
#define GT_SDRAM_OPMODE_OP_MRCE		3	/* Mode Register Cmd enable */
#define GT_SDRAM_OPMODE_OP_CBRCE	4	/* CBR cycle enable */


/* for SDRAM Burst Mode: GT_SDRAM_BURST_MODE */

#define GT_SDRAM_BURST_MODE_MBO		0xFFB	/* reserved bits, must be 1 */
#define GT_BURST_ORDER_SHF		2
#define GT_BURST_ORDER_MSK		(GT_MSK(1) << GT_BURST_ORDER_SHF)
#define GT_BURST_ORDER_BIT		GT_BURST_ORDER_MSK
#define GT_BURST_ORDER_SUBBLOCK		1
#define GT_BURST_ORDER_LINEAR		0


/* for SDRAM Address Decode: GT_SDRAM_ADRS_DEC */

#define GT_ADDRDECODE_DEF		0x2	/* default value */


/* for SDRAM Bank 0/1/2/3 Parameters: GT_SDRAM_BANK*_PARAM */

#define GT_SDRAM_B0_CASLAT_SHF		0
#define GT_SDRAM_B0_CASLAT_MSK		(GT_MSK(2) << GT_SDRAM_B0_CASLAT_SHF)
#define GT_SDRAM_B0_CASLAT_2		1
#define GT_SDRAM_B0_CASLAT_3		2

#define GT_SDRAM_B0_FLOWTHROUGH_SHF	2
#define GT_SDRAM_B0_FLOWTHROUGH_MSK	(GT_MSK(1) << GT_SDRAM_B0_FLOWTHROUGH_SHF)
#define GT_SDRAM_B0_FLOWTHROUGH_BIT	GT_SDRAM_B0_FLOWTHROUGH_MSK
#define GT_SDRAM_B0_FLOWTHROUGH_1_SAMPLE	0
#define GT_SDRAM_B0_FLOWTHROUGH_NO_SAMPLE	1

#define GT_SDRAM_B0_SRASPRCHG_SHF	3
#define GT_SDRAM_B0_SRASPRCHG_MSK	(GT_MSK(1) << GT_SDRAM_B0_SRASPRCHG_SHF)
#define GT_SDRAM_B0_SRASPRCHG_2		0
#define GT_SDRAM_B0_SRASPRCHG_3		1

#define GT_SDRAM_B0_COMPATIBLE_SHF	4 /* for GT64120A's predecessor */
#define GT_SDRAM_B0_COMPATIBLE_MSK	(GT_MSK(1) << GT_SDRAM_B0_COMPATIBLE_SHF)
#define GT_SDRAM_B0_COMPATIBLE_BIT	GT_SDRAM_B0_COMPATIBLE_MSK
#define GT_SDRAM_B0_COMPATIBLE_B1	0
#define GT_SDRAM_B0_COMPATIBLE_B0	1

#define GT_SDRAM_B0_64BITINT_SHF	5
#define GT_SDRAM_B0_64BITINT_MSK	(GT_MSK(1) << GT_SDRAM_B0_64BITINT_SHF)
#define GT_SDRAM_B0_64BITINT_BIT	GT_SDRAM_B0_64BITINT_MSK
#define GT_SDRAM_B0_64BITINT_2		0
#define GT_SDRAM_B0_64BITINT_4		1

#define GT_SDRAM_B0_BANKWIDTH_SHF	6
#define GT_SDRAM_B0_BANKWIDTH_MSK	(GT_MSK(1) << GT_SDRAM_B0_BANKWIDTH_SHF)
#define GT_SDRAM_B0_BANKWIDTH_BIT	GT_SDRAM_B0_BANKWIDTH_MSK
#define GT_SDRAM_B0_BANKWIDTH_32	0
#define GT_SDRAM_B0_BANKWIDTH_64	1

#define GT_SDRAM_B0_BANKLOC_SHF		7
#define GT_SDRAM_B0_BANKLOC_MSK		(GT_MSK(1) << GT_SDRAM_B0_BANKLOC_SHF)
#define GT_SDRAM_B0_BANKLOC_BIT		GT_SDRAM_B0_BANKLOC_MSK
#define GT_SDRAM_B0_BANKLOC_EVEN	0
#define GT_SDRAM_B0_BANKLOC_ODD		1

#define GT_SDRAM_B0_ECC_SHF		8
#define GT_SDRAM_B0_ECC_MSK		(GT_MSK(1) << GT_SDRAM_B0_ECC_SHF)
#define GT_SDRAM_B0_ECC_BIT		GT_SDRAM_B0_ECC_MSK
#define GT_SDRAM_B0_ECC_NOT_SUPPORTED	0
#define GT_SDRAM_B0_ECC_SUPPORTED	1

#define GT_SDRAM_B0_BYPASS_SHF		9
#define GT_SDRAM_B0_BYPASS_MSK		(GT_MSK(1) << GT_SDRAM_B0_BYPASS_SHF)
#define GT_SDRAM_B0_BYPASS_BIT		GT_SDRAM_B0_BYPASS_MSK
#define GT_SDRAM_B0_BYPASS_NO_BYPASS	0
#define GT_SDRAM_B0_BYPASS_BYPASS	1

#define GT_SDRAM_B0_SRASTOSCAS_SHF	10
#define GT_SDRAM_B0_SRASTOSCAS_MSK	(GT_MSK(1) << GT_SDRAM_B0_SRASTOSCAS_SHF)
#define GT_SDRAM_B0_SRASTOSCAS_BIT	GT_SDRAM_B0_SRASTOSCAS_MSK
#define GT_SDRAM_B0_SRASTOSCAS_2	0
#define GT_SDRAM_B0_SRASTOSCAS_3	1

#define GT_SDRAM_B0_SDRAMSIZE0_SHF	11
#define GT_SDRAM_B0_SDRAMSIZE0_MSK	(GT_MSK(1) << GT_SDRAM_B0_SDRAMSIZE0_SHF)
#define GT_SDRAM_B0_SDRAMSIZE0_BIT	GT_SDRAM_B0_SDRAMSIZE0_MSK
#define GT_SDRAM_B0_SDRAMSIZE0_16M	0
#define GT_SDRAM_B0_SDRAMSIZE0_64M	1
#define GT_SDRAM_B0_SDRAMSIZE0_128M	1
#define GT_SDRAM_B0_SDRAMSIZE0_256M	1

#define GT_SDRAM_B0_EXTPARITY_SHF	12
#define GT_SDRAM_B0_EXTPARITY_MSK	(GT_MSK(1) << GT_SDRAM_B0_EXTPARITY_SHF)
#define GT_SDRAM_B0_EXTPARITY_BIT	GT_SDRAM_B0_EXTPARITY_MSK
#define GT_SDRAM_B0_EXTPARITY_NO_GEN	0
#define GT_SDRAM_B0_EXTPARITY_GEN	1

#define GT_SDRAM_B0_BRSTLEN_SHF		13
#define GT_SDRAM_B0_BRSTLEN_MSK		(GT_MSK(1) << GT_SDRAM_B0_BRSTLEN_SHF)
#define GT_SDRAM_B0_BRSTLEN_BIT		GT_SDRAM_B0_BRSTLEN_MSK
#define GT_SDRAM_B0_BRSTLEN_8		0
#define GT_SDRAM_B0_BRSTLEN_4		1

#define GT_SDRAM_B0_SDRAMSIZE1_SHF	14
#define GT_SDRAM_B0_SDRAMSIZE1_MSK	(GT_MSK(1) << GT_SDRAM_B0_SDRAMSIZE1_SHF)
#define GT_SDRAM_B0_SDRAMSIZE1_BIT	GT_SDRAM_B0_SDRAMSIZE1_MSK
#define GT_SDRAM_B0_SDRAMSIZE1_16M	0
#define GT_SDRAM_B0_SDRAMSIZE1_64M	0
#define GT_SDRAM_B0_SDRAMSIZE1_128M	0
#define GT_SDRAM_B0_SDRAMSIZE1_256M	1


/* for Device Bank 0/1/2/3 Parameters: GT_DEV_BANK*_PARAM_OFS */

#define GT_DEV_BANK_TURNOFF_SHF		0
#define GT_DEV_BANK_TURNOFF_MSK		(GT_MSK(3) << GT_DEV_BANK_TURNOFF_SHF)

#define GT_DEV_BANK_ACCTOFIRST_SHF	3
#define GT_DEV_BANK_ACCTOFIRST_MSK	(GT_MSK(4) << GT_DEV_BANK_ACCTOFIRST_SHF)

#define GT_DEV_BANK_ACCTONEXT_SHF	7
#define GT_DEV_BANK_ACCTONEXT_MSK	(GT_MSK(4) << GT_DEV_BANK_ACCTONEXT_SHF)

#define GT_DEV_BANK_ALETOWR_SHF		11
#define GT_DEV_BANK_ALETOWR_MSK		(GT_MSK(3) << GT_DEV_BANK_ALETOWR_SHF)

#define GT_DEV_BANK_WRACTIVE_SHF	14
#define GT_DEV_BANK_WRACTIVE_MSK	(GT_MSK(3) << GT_DEV_BANK_WRACTIVE_SHF)

#define GT_DEV_BANK_WRHIGH_SHF		17
#define GT_DEV_BANK_WRHIGH_MSK		(GT_MSK(3) << GT_DEV_BANK_WRHIGH_SHF)

#define GT_DEV_BANK_DEVWIDTH_SHF	20
#define GT_DEV_BANK_DEVWIDTH_MSK	(GT_MSK(2) << GT_DEV_BANK_DEVWIDTH_SHF)
#define GT_DEV_BANK_DEVWIDTH_8		0
#define GT_DEV_BANK_DEVWIDTH_16		1
#define GT_DEV_BANK_DEVWIDTH_32		2
#define GT_DEV_BANK_DEVWIDTH_64		3

#define GT_DEV_BANK_DMAFLYBY0_SHF	22
#define GT_DEV_BANK_DMAFLYBY0_MSK	(GT_MSK(1) << GT_DEV_BANK_DMAFLYBY0_SHF)
#define GT_DEV_BANK_DMAFLYBY0_BIT	GT_DEV_BANK_DMAFLYBY_MSK

#define GT_DEV_BANK_DEVLOC_SHF		23
#define GT_DEV_BANK_DEVLOC_MSK		(GT_MSK(1) << GT_DEV_BANK_DEVLOC_SHF)
#define GT_DEV_BANK_DEVLOC_BIT		GT_DEV_BANK_DEVLOC_MSK
#define GT_DEV_BANK_DEVLOC_EVEN		0
#define GT_DEV_BANK_DEVLOC_ODD		1

#define GT_DEV_BANK_DMAFLYBY1_SHF	26
#define GT_DEV_BANK_DMAFLYBY1_MSK	(GT_MSK(4) << GT_DEV_BANK_DMAFLYBY1_SHF)


/* for PCI Command: PCI_0_COMMAND, PCI_1_COMMAND */

#define GT_MBYTESWAP_SHF		0
#define GT_MBYTESWAP_MSK		(GT_MSK(1) << GT_MBYTESWAP_SHF)
#define GT_MBYTESWAP_BIT		GT_MBYTESWAP_MSK
#define GT_MBYTESWAP_SWAP		0
#define GT_MBYTESWAP_DONT_SWAP		1

#define GT_SYNCMODE_SHF			1
#define GT_SYNCMODE_MSK			(GT_MSK(3) << GT_SYNCMODE_SHF)
#define GT_SYNCMODE_BIT			GT_SYNCMODE_MSK
#define GT_SYNCMODE_DC_TO_66		0
#define GT_SYNCMODE_P_GE_HALF_T		1
#define GT_SYNCMODE_SYNC_P_GE_HALF_T	2
#define GT_SYNCMODE_P_GE_THIRD_T	5
#define GT_SYNCMODE_SYNC_P_GE_THIRD_T	6

#define GT_MWORDSWAP_SHF		10
#define GT_MWORDSWAP_MSK		(GT_MSK(1) << GT_MWORDSWAP_SHF)
#define GT_MWORDSWAP_BIT		GT_MWORDSWAP_MSK
#define GT_MWORDSWAP_SWAP		1
#define GT_MWORDSWAP_DONT_SWAP		0

#define GT_SWORDSWAP_SHF		11
#define GT_SWORDSWAP_MSK		(GT_MSK(1) << GT_SWORDSWAP_SHF)
#define GT_SWORDSWAP_BIT		GT_SWORDSWAP_MSK
#define GT_SWORDSWAP_SWAP		1
#define GT_SWORDSWAP_DONT_SWAP		0

#define GT_SSBWORDSWAP_SHF		12
#define GT_SSBWORDSWAP_MSK		(GT_MSK(1) << GT_SSBWORDSWAP_SHF)
#define GT_SSBWORDSWAP_BIT		GT_SSBWORDSWAP_MSK
#define GT_SSBWORDSWAP_SWAP		1
#define GT_SSBWORDSWAP_DONT_SWAP	0

#define GT_SBYTESWAP_SHF		16
#define GT_SBYTESWAP_MSK		(GT_MSK(1) << GT_SBYTESWAP_SHF)
#define GT_SBYTESWAP_BIT		GT_SBYTESWAP_MSK
#define GT_SBYTESWAP_SWAP		0
#define GT_SBYTESWAP_DONT_SWAP		1


/* for PCI Timeout & Retry: GT_PCI0_TIMEOUT_RETRY, GT_PCI1_TIMEOUT_RETRY */

#define GT_TIMEOUT0_SHF			0
#define GT_TIMEOUT0_MSK			(GT_MSK(8) << GT_TIMEOUT0_SHF)
#define GT_TIMEOUT0_MAX			GT_TIMEOUT0_MSK
#define GT_TIMEOUT0_DEF			0x0f

#define GT_TIMEOUT1_SHF			8
#define GT_TIMEOUT1_MSK			(GT_MSK(8) << GT_TIMEOUT1_SHF)
#define GT_TIMEOUT1_MAX			GT_TIMEOUT1_MSK
#define GT_TIMEOUT1_DEF			0x07

#define GT_RETRYCTR_SHF			16
#define GT_RETRYCTR_MSK			(GT_MSK(8) << GT_RETRYCTR_SHF)
#define GT_RETRYCTR_MAX			GT_RETRYCTR_MSK
#define GT_RETRYCTR_RETRY_FOREVER	0
#define GT_RETRYCTR_DEF			GT_RETRYCTR_RETRY_FOREVER

#define GT_TIMEOUT_MAX	(GT_TIMEOUT0_MAX | GT_TIMEOUT1_MAX | GT_RETRYCTR_MAX)


/* for PCI configuration cycles: GT_PCI0_CFG_ADRS, GT_PCI1_CFG_ADRS */

#define GT_CONFIGEN_SHF			31
#define GT_CONFIGEN_MSK			(GT_MSK(1) << GT_CONFIGEN_SHF)
#define GT_CONFIGEN_BIT			GT_CONFIGEN_MSK

#define GT_BUSNUM_SHF			16
#define GT_BUSNUM_MSK			(GT_MSK(8) << GT_BUSNUM_SHF)

#define GT_DEVNUM_SHF			11
#define GT_DEVNUM_MSK			(GT_MSK(5) << GT_DEVNUM_SHF)

#define GT_FUNCNUM_SHF			8
#define GT_FUNCNUM_MSK			(GT_MSK(3) << GT_FUNCNUM_SHF)

#define GT_REGNUM_SHF			2
#define GT_REGNUM_MSK			(GT_MSK(6) << GT_REGNUM_SHF)


/*
 * for Interrupt Cause & Mask: GT_INTR_CAUSE, GT_CPU_INTR_MASK,
 * GT_PCI0_INTR_CAUSE_MASK
 *
 * (1) can also be used for High Interrupt Cause & Mask: GT_H_INTR_CAUSE,
 * GT_CPU_H_INTR_MASK, GT_PCI0_H_INTR_CAUSE_MASK
 */

#define GT_INTR_INTSUM			0x00000001
#define GT_INTR_MEMOUT			0x00000002
#define GT_INTR_DMAOUT			0x00000004
#define GT_INTR_CPUOUT			0x00000008
#define GT_INTR_DMA0COMP		0x00000010
#define GT_INTR_DMA1COMP		0x00000020
#define GT_INTR_DMA2COMP		0x00000040
#define GT_INTR_DMA3COMP		0x00000080
#define GT_INTR_T0EXP			0x00000100
#define GT_INTR_T1EXP			0x00000200
#define GT_INTR_T2EXP			0x00000400
#define GT_INTR_T3EXP			0x00000800
#define GT_INTR_MASRDERR		0x00001000	/* (1) */
#define GT_INTR_SLVWRERR		0x00002000	/* (1) */
#define GT_INTR_MASWRERR		0x00004000	/* (1) */
#define GT_INTR_SLVRDERR		0x00008000	/* (1) */
#define GT_INTR_ADDRERR 		0x00010000	/* (1) */
#define GT_INTR_MEMERR			0x00020000
#define GT_INTR_MASABORT		0x00040000	/* (1) */
#define GT_INTR_TARABORT		0x00080000	/* (1) */
#define GT_INTR_RETRYCTR		0x00100000	/* (1) */
#define GT_INTR_PMCINT			0x00200000	/* (1) */

#define GT_INTR_CPUINT_SHF		22
#define GT_INTR_CPUINT_MSK		(GT_MSK(4) << GT_CPUINT_SHF)

#define GT_INTR_PCIINT_SHF		26
#define GT_INTR_PCIINT_MSK		(GT_MSK(4) << GT_PCIINT_SHF)

#define GT_INTR_CPUINTSUM		0x40000000
#define GT_INTR_PCIINTSUM		0x80000000


/* for SErr0/1* Mask, PCI_0/1 Events: GT_PCI0_SERR0_MASK, GT_PC1_SERR1_MASK */

#define GT_SERR_ADDRERR			0x00000001
#define GT_SERR_MASWRERR		0x00000002
#define GT_SERR_MASRDERR		0x00000004
#define GT_SERR_MEMERR			0x00000008
#define GT_SERR_MASABORT		0x00000010
#define GT_SERR_TARABORT		0x00000020


/* Miscellenous */

#define GT_BANKSIZE_MAX		(256 * 1024 * 1024)   /* Max 256MB bank */

/* GT Internal register data must be swapped when CPU is in big-endian mode */

#if (_BYTE_ORDER == _BIG_ENDIAN)
#define GT_SWAP(x)			LONGSWAP(x)
#else /* _BYTE_ORDER == _LITTLE_ENDIAN */
#define GT_SWAP(x)			(x)
#endif /* _BYTE_ORDER */

#ifdef __cplusplus
}
#endif

#endif	/* __INCgt64120ah */
